In a semiconductor fabrication process, i.e., for memory devices, numerous metal interconnects and vias are used to provide electrical communication between various devices constructed on a semiconductor wafer which are insulated by inter-metal dielectric layers. In conventional devices, only one or two levels of such metal conducting layers are necessary for connecting the devices on various layers. However, modern high-capacity memory devices demand as many as five or six metal interconnect layers for completing the circuits of the memory device. The inter-metal dielectric (IMD) layers are normally formed of an insulating material such as silicon oxide. Each layer of the insulating material is planarized before the formation of the next layer device and the deposition of the inter-metal dielectric layer. This is shown in FIG. 1 for a conventional memory device that has two layers of metal interconnects.
Referring initially to FIG. 1, wherein a memory device 10 that is built on a silicon substrate 12 is shown. On top of the silicon substrate 12, a first level metal 14 is deposited for establishing electrical communication with devices built in the silicon substrate 12. A first inter-metal dielectric layer 16 is then used to insulate the first level metal 14. Metal studs 20 are then provided for establishing electrical communication with the next level devices. After the first level IMD 16 is planarized, a second level metal 22 is deposited and patterned for connection to the metal studs 20. A second level IMD 26 is then formed of an oxide material to further insulate the second level metal 22. After the formation of the metal studs 28 and the planarization of the second IMD layer 26, a third and final metal layer is deposited and formed into metal lines 30. On top of the metal lines 30, a final passivation layer 32 is deposited to insulate the metal lines 30.
The final insulating layer 32 is frequently formed of two insulating materials, i.e., first a silicon oxide layer (not shown) for insulating purpose, and then a silicon nitride layer (not shown) for use as a moisture barrier. The silicon oxide layer is frequently deposited to a thickness of about 2,000 .ANG., while the silicon nitride layer is frequently deposited to a thickness of about 7,000 .ANG.. This is shown at locations 34 and 38 in FIG. 2.
In a chemical vapor deposition process for depositing silicon oxide and silicon nitride, the thicknesses of the insulating layers deposited on the sidewall portions of the metal lines 30 are frequently inadequate. This is especially true when the metal lines are closely positioned together. When an inadequate thickness of the insulating layers is deposited on the sidewalls of the metal lines, a cavity or a pin-hole 36 can be formed. The pin-hole 36 is normally of a very small size and cannot be observed by visual examination.
A conventional method that has been used for detecting cavities or pin-holes in an insulating layer deposited on top of a semiconductor substrate is shown in FIG. 3. A fluid reservoir 50 that is frequently constructed of an electrically conductive material such as metal is first provided. Into the fluid reservoir 50, an electrolyte 52 is filled to near the top of the reservoir. A pre-processed semiconductor wafer 56 which has a passivation layer deposited on top is then placed on the bottom of the reservoir 50 in contact with the electrically conductive material of the reservoir. The wafer 56 is therefore electrically connected to the fluid reservoir and functions as a bottom electrode in an electrolysis reaction later performed.
Into the electrolyte solution 52, and above the immersed semiconductor wafer 56, is placed a metal wire 60 which functions as a top electrode. The dimension of the circular-shaped wire is approximately 1 cm in diameter. The metal wire 60, which is electrically conductive, is then connected to one end 62 of a DC power supply 64. The other end 66 of the DC power supply 64 is then connected to the fluid reservoir 50 such that electrical current flows through the wafer 56 and the electrolyte 52 to the top electrode 60. A suitable DC voltage used can be 10 volts, even though other suitable voltages may also be used.
The principle of operation for the apparatus shown in FIG. 3 can be explained as follows. When a cavity or a pin-hole (3 6 as shown in FIG. 2) exists in the passivation layer on the wafer 56, the metal line 30, which is frequently formed of an aluminum material under the passivation layer 32 is exposed to the outside environment through pin-hole 36. The aluminum surface exposed at pin-hole 36 therefore acts as a bottom electrode to establish a current flow between pin-hole 36 and the top electrode 60. The electrolyte solution, which is frequently a mixture of isopropyl alcohol and deionized water, at the site of the pin-hole 36 undergoes an electrolysis reaction by producing hydrogen and oxygen gases in bubble form. An optical microscope is then used to observe a string of bubbles produced at the pin-hole to surface in the electrolyte solution. The locations of the pin-holes can thus be identified.
The conventional apparatus illustrated in FIG. 3 is crude and does not function properly for several reasons. First, the electric field generated by the metal wire 60 used as a top electrode is not uniform. The field is stronger at locations closer to the wire and weak at the center of the circle. This leads to a problem that electrolysis reaction may not occur where the electric field is weak. Secondly, the metal wire 60 used is not transparent, and as such, the portion of the wafer that is directly under the wire can not be observed. Some of the bubble formation may not be apparent when it occurs directly under or near a metal wire to an observer. Thirdly, on the surface of the semiconductor wafer 56, there also exists numerous bonding pads which are exposed metal that generates bubbles during the examination for pin-holes. When a pin-hole exists at or near a bonding pad location, the metal wire frequently blocks the view and makes it more difficult to observe any pin-holes since bubbles from a bonding pad and bubbles from a pin-hole can not be distinguished. The conventional apparatus and method for detecting pin-holes in a passivation layer therefore needs much improvement for it to be used as a reliable quality control method.
It is therefore an object of the present invention to provide a method for detecting cavities in an insulating layer deposited over a conductive layer does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for detecting pin-holes in a passivation layer deposited over a metal line on a semiconductor wafer that is reliable, and accurate.
It is a further object of the present invention to provide a method for detecting pin-holes in a passivation layer deposited over a metal line on a semiconductor wafer that is based on an electrolysis reaction during which bubbles are produced at pin-hole locations.
It is still another object of the present invention to provide a method for detecting pin-holes in a passivation layer deposited over a metal line on a semiconductor wafer that utilizes a substantially transparent, conductive film as an upper electrode for the easy observation of bubble formation during an electrolysis reaction occurring at the pin-hole site.
It is yet another object of the present invention to provide a method for detecting pin-holes in a passivation layer deposited over a metal line on a semiconductor wafer by utilizing a clear, conductive film as an upper electrode and a mixture of isopropyl alcohol and deionized water as an electrolyte.
It is another further object of the present invention to provide a method for detecting pin-holes in a passivation layer deposited over a metal conductor layer on a semiconductor wafer by utilizing an upper electrode formed by depositing metal particles on a clear glass plate.
It is still another further object of the present invention to provide an apparatus for detecting pin-holes in a passivation layer deposited over a metal conductor layer on a semiconductor wafer incorporating an improved upper electrode that is a substantially transparent and conductive film.